Compositions and methods for planarizing or polishing the surface of a substrate, especially for chemical-mechanical polishing (CMP), are well known in the art. Polishing compositions (also known as polishing slurries) used in CMP processes typically contain an abrasive material in an aqueous solution and are applied to a surface by contacting the surface with a polishing pad saturated with the polishing composition. Typical abrasive materials include aluminum oxide, cerium oxide, silicon dioxide, and zirconium oxide. The polishing composition typically is used in conjunction with a polishing pad (e.g., polishing cloth or disk). The polishing pad may contain abrasive material in addition to, or instead of, the abrasive material in the polishing composition.
Silicon dioxide-based inter-metal dielectric layers are frequently used to isolate metal-containing circuit lines formed on a substrate. Polishing compositions for these silicon dioxide-based inter-metal dielectric layers have been particularly well developed in the semiconductor industry, and the chemical and mechanical nature of polishing and wear of the silicon dioxide-based dielectrics is reasonably well understood. One problem with the silicon dioxide-based dielectric materials, however, is that their dielectric constant is relatively high, being approximately 3.9 or higher, depending on factors such as residual moisture content. As a result, the capacitance between the conductive layers is also relatively high, which in turn limits the speed (frequency) at which a circuit can operate. Strategies being developed to increase the frequency at which the circuit can operate include (1) using metals having lower resistivity values (e.g., copper) to form the circuit lines and (2) providing electrical isolation with insulating materials having lower dielectric constants relative to silicon dioxide.
One way to fabricate planar copper circuit traces on a dielectric substrate is referred to as the damascene process. In accordance with this process, the silicon dioxide dielectric surface is patterned by a conventional dry etch process to form holes (i.e., vias) and trenches for vertical and horizontal interconnects prior to deposition of copper onto the surface. Copper has the property of being a fast diffuser during the thermal cycling that a semiconductor substrate experiences during the fabrication process, as well as during actual device operation under applied electric fields, and can move quickly through the underlying dielectric layer and overlying interlevel dielectric (ILD) layers to “poison” the device. Copper diffusion through the substrate dielectric material results in current leakage between adjacent metal lines, leading to degraded device characteristics and, potentially, non-functioning devices. Thus, a diffusion barrier layer is typically applied to the substrate before deposition of copper. Tantalum and tantalum nitride have found wide acceptance in the industry as barrier layer materials and are typically applied to a substrate by physical vapor deposition (PVD). The diffusion barrier layer is provided with a copper seed layer and then over-coated with a copper layer from a copper plating bath. Chemical-mechanical polishing is employed to reduce the thickness of the copper over-layer, as well as to remove the diffusion barrier layer lying outside of the holes and trenches, until a planar surface that exposes elevated portions of the dielectric surface is obtained. The vias and trenches remain filled with electrically conductive copper forming the circuit interconnects.
Typically, at least two polishing steps are utilized in the manufacturing process in which a first polishing step removes most of the copper overburden, and a subsequent polishing step removes barrier material to expose the underlying dielectric layer. The increasing use of insulating materials having lower dielectric constants relative to silicon dioxide, often referred to as “low-κ dielectrics,” leads to new challenges in the development of new polishing compositions and methods. Low-κ dielectric materials, which include porous metal oxide, porous or non-porous carbon doped silicon oxide, and fluorine-doped silicon oxide, are typically softer and more brittle than conventional silicon oxide-based dielectric materials. Development of polishing compositions that are effective in removing tantalum-based barrier materials and also soft low-κ dielectric materials is thus complicated. In addition, the chemistry of low-κ dielectric materials differs from that of conventional silicon oxide-based dielectric materials, often exhibiting unacceptably low removal rates when polished with conventional chemical-mechanical polishing compositions.
Moreover, in some schemes, the soft low-κ dielectric materials are capped with harder conventional silicon dioxide-based dielectric materials to allow for greater control over planarization. The capping dielectric also must be removed during polishing to expose the underlying low-κ dielectric material. Polishing compositions that can remove conventional silicon dioxide-based dielectric materials and low-κ dielectric materials at comparable rates are therefore desirable.